The present disclosure relates to the design of clock grids, and more specifically, to methods and computer program products for facilitating the design of clock grids in integrated circuits.
Clock grids are commonly used for the distribution of clock signals in both high performance processor designs as well in designs for application specific integrated circuits (ASICs) with frequencies over one gigahertz (GHz). One component of clock grid design is the design of a virtual grid that is used to route the clock pins of leaf level clock buffers, which are typically located at a lowest level of hierarchy of an integrated circuit, to the global clock grid, which is typically located at the highest level of hierarchy of an integrated circuit. The virtual grid includes reserved metal tracks which are propagated and managed across the hierarchy of the integrated circuit by multiple designers that are each responsible for a different portion of the hierarchy, such as a macro level design, an integration level design, and a clock design. In general, the design process can be tedious, cumbersome and error-prone because of the need for several iterations between the designers at the different levels of hierarchy of the integrated circuit.
Currently, design of a lower level of an integrated circuit, or macro, of a hierarchy involves routing the clock signals from the input pins of leaf level clock buffers to a specific metal layer of the integrated circuit hierarchy independent of the ceiling layer of the macro. Accordingly, the virtual grid is managed as blockage which the macro designer needs to avoid and work around. For various reasons, it is not always possible for the macro designer to avoid or work around these blockages. For example, elements in the macro may conflict with the reserved virtual grid, the virtual grid may be overly pessimistic in areas of only a few or no clock sinks, or the virtual grid may be non-existent in areas where clock sinks exist. In these cases, the macro designers have to communicate to the integrators what modifications and customizations of the virtual grid are needed based on the macro design requirements. Multiple iterations and changes across the different hierarchical entities may be required to achieve a virtual grid that works around the specifics of the macro design.